Several applications exist, in personal computers and other systems, for a circuit which provides a divide-by-two output from the internal clock of the computer which accurately tracks an undivided clock signal without skew between the two signals. Thus, the rising edges (and, preferably, also the trailing edges) of the signal from the divide-by-two circuit coincides with the corresponding rising edges (and trailing edges) of signals at the frequency of the clock, as applied to circuitry within the system driven by the two different signals.
In the past, to provide a simultaneous divide-by-one and divide-by-two clock output from a master source clock, with less than 0.5 nanoseconds between resulting edges of the respective signals, the master clock has been applied to a "D" type flip-flop externally wired as a divide-by-two device, and to a similarly constructed latch wired to directly pass through the master clock signal. The reason for using the second latch for passing through the master clock to provide the divide-by-one output is an attempt to match the circuit paths for the signals. This is done so that processing variations are nearly identical for both circuit paths, with the resultant outputs ideally coinciding with one another (that is, without skew). In reality, however, the output of the divide-by-one latch is skewed with respect to the divide-by-two flip-flop. To compensate for this, the divide-by-one output is connected to one or more inverters, the outputs of which are unconnected or "open". These inverters operate to provide a capacitive load on the output of the divide-by-one latch to match the delays in this flip-flop with those of the divide-by-two flip-flop for one process and one set of process parameters. A problem which exists, however, is that when the circuit is subjected to variations in operating parameters, such as operating temperatures, the amount of skew varies considerably; so that elimination of skew requires specific tuning or adjustment of the circuitry in the operating environment. Frequently, this cannot be done; and even if such adjustments are possible, the necessity for new adjustments, as conditions change, constantly is necessary.
It is desirable to provide a CMOS clock divider circuit which is designed so that the divide-by-one and divide-by-two circuit paths automatically inherently track one another, substantially reducing skew between the two signals.